Latency Insertion Method (LIM)

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 LIM is the first circuit simulator that exhibits linear numerical complexity This is achieved by using the latency insertion method, an algorithm that uses a leapfrog between current and voltage calculations. Traditional circuit simulators exhibit super-linear numerical complexity. LIM’s advantage increases dramatically with the size of the network. This implementation of LIM offers both linear and nonlinear elements and devices and will handle frequency-dependent elements via macro-modeling. This makes it a universal tool for transient verification at all the levels of integration, chip, package, board and backplane. 

IC verification can be quite time-consuming for systems consisting of tens of millions of transistors. In addition, total interconnect lengths are in the order of several kilometers within the chip. The level of complexity. With the development of advanced transistor models for the higher technology nodes, LIM is the primary approach for speedy and accurate verification.

IR Drop is a signal integrity(SI) problem caused by wire resistance. In integrated circuits, it leads to a non-uniform distribution of the voltages on the power supply rails Vdd and Vss. Dynamic IR drops can lead to unacceptable voltage levels leading to ground bounce. The LIM simulator is well-suited for the prediction of both static and dynamic IR drops at the IC, package and board levels. For large nets, LIM will outperform conventional simulators by almost two orders for magnitude.

Phase-Locked Loops (PLL) are critical subsystems in many communication circuits, computing systems, military equipment such as radar systems, medical-related equipment. All of these systems incorporate PLLs either for clock generation or signal generation purposes. PLLs are strong nonlinear feed-back systems that exhibit complex dynamics with large bandwidth. Such systems are very sensitive to noise. Transistor-level PLL simulations can be slow due to the dual time scale requirement necessitating a very small time step over a very long simulation time. Such condition is perfectly suited for the LIM simulator.

 With the LIM simulator, lock acquisition in a PLL can be accurately captured with the inclusion of all transistor effects. External (random or malicious) interference from electromagnetic interference (EMI) or radio-frequency interference (RFI) and their disruptive effects such as the pulling of the local-oscillator or the unlocking of the the voltage-controlled oscillator (VCO) from the reference signal. 

At the pre-layout stage, information about the circuit is available in the form of a floorplan, pad out, and current and voltage budgets. The model for power integrity analysis is then built based on the process parameters, supply voltage values, required current loads, general geometry, and the floor plan can potentially be fatal for the product, thus requiring a complete redesign and leading to unacceptable time-to-market delays.

Verification of logic blocks such as ripple carry adder and RAMs is important prior to tape-out. This allows designers to assess waveform distortion, estimate delays and determine whether logic levels are actually achieved. With the development of advanced transistor models for the higher technology nodes, LIM is the primary approach for speedy and accurate verification. Speedup factor in verification is increased as the size of the circuit becomes larger.